AT87251G2D-3CSUM【PDF 10/77 页】IC 8051 MCU 32K OTP 24MHZ 40DIP

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AT/TSC8x251G2D

4135F–8051–11/06

Table 11.

Configuration Byte 0

UCONFIG0

Notes: 1. UCONFIG0 is fetched twice so it can be properly read both in Page or Non-Page

modes. If P2.1 is cleared during the first data fetch, a Page mode configuration is

used, otherwise the subsequent fetches are performed in Non-Page mode.

2. This selection provides compatibility with the standard 80C51 hardware which is mul-

tiplexing the address LSB and the data on Port 0.

7654

3210

WSA1#

WSA0#

XALE#

RD1

RD0

PAGE#

SRC

Bit Number

Bit

Mnemonic

Description

Reserved

Set this bit when writing to UCONFIG0.

6WSA1#

Wait State A bits

Select the number of wait states for RD#, WR# and PSEN# signals for external

memory accesses (all regions except 01:).

WSA1#

WSA0#

Number of Wait States

5WSA0#

4XALE#

Extend ALE bit

Clear to extend the duration of the ALE pulse from TOSC to 3TOSC.

Set to minimize the duration of the ALE pulse to 1TOSC.

RD1

Memory Signal Select bits

Specify a 18-bit, 17-bit or 16-bit external address bus and the usage of RD#,

WR# and PSEN# signals (see Table 13).

RD0

1PAGE#

Page Mode Select bit(1)

Clear to select the faster Page mode with A15:8/D7:0 on Port 2 and A7:0 on

Port 0.

Set to select the non-Page mode(2) with A15:8 on Port 2 and A7:0/D7:0 on Port

0SRC

Source Mode/Binary Mode Select bit

Clear to select the binary mode.

Set to select the source mode.

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